Digital Capacitance Meter
20-Year-Old Breadboard Project Reconstruction
Original Concept & Design Overview
Core Principle: This digital capacitance meter operates on the "reverse frequency counter" principle. Instead of a fixed gate time measuring variable frequency, the unknown capacitor (Cx) controls the gate duration of a 555 timer, during which a stable clock frequency is counted by cascaded 7490 decade counters. The resulting count is proportional to capacitance.
Count (N) = fclock × tgate
Where tgate = 1.1 × Rx × Cx
Solution: Cx = (N × 1.1) / (fclock × Rx)
Key Components:
- 2× NE555 timers (clock oscillator + gate generator)
- 4× 7490 decade counters (0000-9999 BCD count)
- 4× HP 5082-7300 7-segment(dot-matrix) displays (with latch)
- 1× CD4017 decade counter (sequence controller)
- Calibration potentiometer (10kΩ, clock timing network)
4017 Sequencing Mechanism
The CD4017 provides the critical COUNT → LATCH → CLEAR → REPEAT sequence, automatically advancing on each measurement completion.
| State | 4017 Output | Action | Duration |
|---|---|---|---|
| Q0 | Pin 2 HIGH | COUNT: 7490s enabled, incrementing during gate | tgate = 1.1 × Rx × Cx |
| Q1 | Pin 4 HIGH | LATCH: Displays capture current count | ~50ms (hold time) |
| Q2 | Pin 7 HIGH | CLEAR: 7490s reset to 0000 | ~10ms (reset pulse) |
| Q3 | Pin 10 HIGH | RESET: 4017 returns to Q0, ready for next measurement | Immediate |
Calibration System & Empirical Method
Primary Calibration: 10kΩ potentiometer in clock 555 timing network (pins 7-2/6), adjusting frequency from 50-200kHz for full range coverage (10pF to 10µF).
Original Calibration Methodology
The builder employed a sophisticated empirical approach, rejecting inconsistent substitution box values in favor of real, labeled capacitors sorted by nominal value. Calibration targeted the minimax error across the measurement range:
Midpoint Strategy: Perfect accuracy at 1nF reference, accepting ±20% outliers at extremes
Result: Typical ±5% accuracy, excellent for 1980s discrete design
| Reference Cap | Measured Value | Error | Notes |
|---|---|---|---|
| 10pF ceramic | 12pF (+20%) | Outlier (low end) | Stray capacitance dominant |
| 100pF ceramic | 105pF (+5%) | Excellent | |
| 1nF ceramic | 1000pF (0%) | Reference point | Calibration sweet spot |
| 10nF ceramic | 10.8nF (+8%) | Good | |
| 100nF ceramic | 120nF (+20%) | Outlier (high end) | Large value nonlinearity |
Corrections & Refinements
- 4017 Reset: Confirmed Q3 (pin 10) → MR (pin 11) with pull-up creates self-resetting three-state sequence
- Calibration Location: Clock 555 pot provides linear scaling across full range vs. gate timing's limited adjustment
- Trigger Mechanism: Gate 555 /Q falling edge precisely times 4017 advance at measurement completion
- Empirical Validation: Midpoint calibration methodology superior to theoretical values, compensating for breadboard parasitics