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AT28C64-15PC AT28C64-15PI DIP-28 ATMEL
robotic.icu: AT28C64-15PC AT28C64-15PI DIP-28 ATMEL
Posted in: Specs | by Brian Taylor | 2018 Oct 08
AT28C64-15PC
8 bit eeprom
AT28C64-15PC AT28C64-15PI DIP-28 ATMEL

I bought of these on ebay for the raspberry pi which I plan to get soon!

Item:
AT28C64-15PC AT28C64-15PI DIP-28 ATMEL

Quantity:10pcs
Delivery:10-19, 11-08
Features, Applications:
Features Fast Read Access Time ­ 120 ns Fast Byte Write or 1 ms Self-timed Byte Write Cycle

Internal Address and Data Latches, Internal Control Timer, Automatic Clear Before Write Direct Microprocessor Control, READY/BUSY Open Drain Output, DATA Polling Low Power 30 mA Active Current 100 µA CMOS Standby Current High Reliability, Endurance: or 105 Cycles, Data Retention: 10 Years ± 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-wide Pinout Commercial and Industrial Temperature Ranges

Description

The is a low-power, high-performance 8,192 words by 8-bit nonvolatile electrically erasable and programmable read only memory with popular, easy-to-use features. The device is manufactured with Atmel's reliable nonvolatile technology. (continued)

Pin Name - I/O7 RDY/BUSY NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs Ready/Busy Output No Connect Don't Connect TSOP Top View

Note: PLCC package pins 1 and 17 are DON'T CONNECT.

The AT28C64 is accessed like a Static RAM for the read or write cycles without the need for external components. During a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of a write cycle, the device will to a busy state and automatically clear and write the latched data using an internal control timer. The device includes two methods for detecting the end of a write cycle, level detection of RDY/BUSY (unless pin 1 is N.C.) and DATA Polling of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. The CMOS technology offers fast access times ns at low power dissipation. When the chip is deselected the standby current is less than 100 µA. Atmel's AT28C64 has additional features to ensure high quality and manufacturability. The device utilizes error correction internally for extended endurance and for improved data retention characteristics. An extra 32 bytes of EEPROM are available for device identification or tracking.

Temperature under Bias................................ to +125°C
Storage Temperature..................................... to +150°C
All Input Voltages (including NC Pins) with Respect to +6.25V
All Output Voltages with Respect Ground.............................-0.6V to VCC + 0.6V
Voltage on OE and A9 with Respect to +13.5V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

READ: The AT28C64 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in a high impedance state whenever OE is high. This dual line control gives designers increased flexibility in preventing bus contention. BYTE WRITE: Writing data into the AT28C64 is similar to writing into a Static RAM. A low pulse on the or CE input with OE high and or WE low (respectively) initiates a byte write. The address location is latched on the falling edge of WE (or CE); the new data is latched on the rising edge. Internally, the device performs a self-clear before write. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. FAST BYTE WRITE: The AT28C64E offers a byte write time 200 µs maximum. This feature allows the entire device to be rewritten in 1.6 seconds. READY/BUSY: Pin is an open drain RDY/BUSY output that can be used to detect the end of a write cycle. RDY/BUSY is actively pulled low during the write cycle and is released at the completion of the write. The open drain connection allows for OR-tying of several devices to the same RDY/BUSY line. The RDY/BUSY pin is not connected for the AT28C64X. DATA POLLING: The AT28C64 provides DATA Polling to signal the completion of a write cycle. During a write cycle, an attempted read of the data being written results in the complement of that data for I/O 7 (the other outputs are indeterminate). When the write cycle is finished, true data appears on all outputs. WRITE PROTECTION: Inadvertent writes to the device are protected against in the following ways: (a) VCC sense, if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power on delay, once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a byte write; and (c) write inhibit, holding any one of OE low, CE high or WE high inhibits byte write cycles. CHIP CLEAR: The contents of the entire memory of the AT28C64 may be set to the high state by the CHIP CLEAR operation. By setting CE low and to 12 volts, the chip is cleared when a 10 msec low pulse is applied to WE. A TI EEPROM memory are available to the user for device identification. By raising ± 0.5V and using address locations to 1FFFH the additional bytes may be written to or read from in the same manner as the regular memory array.
Specs

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